The present invention relates to a complementary MOS transistor crystal oscillator circuit and, more particularly, to a low voltage compensator for a power supply in a complementary MOS transistor crystal oscillator circuit.
A C-MOS circuit is conventionally used in an electronic device which requires low power dissipation, especially, in an electronic wristwatch employing a battery of low capacitance.
In an electronic timepiece, a C-MOS crystal oscillator circuit is usually employed, in which a large part of power of the total power dissipation is consumed, because the C-MOS crystal oscillator circuit operates at the highest frequency in the electronic timepiece. Therefore, it is required to reduce the power dissipation at the C-MOS crystal oscillator circuit in order to minimize the total power dissipation in the electronic timepiece.
To this end, it has been proposed to connect a resistor to the source of the transistor included within a C-MOS inverter employed in the crystal oscillator circuit, thereby limiting the current flowing through the C-MOS inverter. However, a voltage V.sub.D applied to the C-MOS inverter is unavoidably decreased by a voltage reduction V.sub.S at the resistor. That is, V.sub.D = V.sub.DD - V.sub.S, when a power supply level is V.sub.DD and the V.sub.SS is maintained at ground potential. Therefore, the permissible low voltage for the C-MOS inverter must be selected at a level lower than that of the crystal oscillator circuit by the voltage reduction V.sub.S at the resistor connected to the source of the C-MOS inverter. This results in a requirement that the gain of the C-MOS inverter must be considerably high. The transistors required for obtaining a high gain enclosed within the C-MOS inverter take up a large amount of space.